CMOS Latch-Up

۷۹.۲ K


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The CMOS structure is analyzed and the PNP and NPN latching transistors are identified. The CMOS latch schematic is drawn and the triggering methods are discussed. Some ways to reduce latch up are presented.

Published by: booksofscience
Published at: ۸ years ago
Category: علمی و تکنولوژی